Strained Silicon Technology for Low - Power High - Speed Circuit Applications

One of the principal economic drivers for the semiconductor industry is high performance, low power applications for the portable electronics consumer market. Unfortunately, the power dissipation resulting from the use of conventional CMOS technology in this area is becoming a critical design issue. Supply voltage reduction has been the preferred technique for reducing power dissipation. However, the associated compromise comes in the form of a drastic increase in circuit delay. Silicon technology based contemporary circuit design research is struggling extremely hard to continue the ‘scaling process’ to satisfy the criteria of low static power dissipation, while maintaining high-speed operation to meet the demands of the market place demands. However, it is accepted that scaling cannot continue indefinitely and other approaches such as new materials and device structures need to be devised to circumvent the inevitable barriers to the reduction in device dimensions. A potential candidate to meet the criteria of low static power dissipation while maintaining high-speed operation is strained silicon (strained-Si) due to its high current drive capability attained through band gap engineering. This thesis explores the applicability of this technology to low-power and high-speed digital and analogue designs by analyzing the power and performance characteristics of a range of circuits. Overall, it was found that strained-Si technology offered improved performance and power dissipation when compared with conventional bulk CMOS. For example, strained-Si devices could operate with supply voltages closer to the threshold voltage than bulk CMOS thus reducing the dynamic power dissipation in circuits. Furthermore, with reduced supply voltage the noise characteristics of the circuit were not significantly impaired. Also for the same power dissipation as a bulk CMOS circuit an improved performance level was achieved in strained-Si. These advantages can be realised without any major changes being required in the standard bulk CMOS process; this also includes the ability to vary the percentage strain in the channel thus permitting the device characteristics to be tailored to suit power/performance requirements for a given application which can be quite diverse. As devices dimensions are scaled down, process variations can have a dramatic effect on the overall circuit performance. The impact of process variability on particular design parameters on several strained-Si circuits was investigated using two statistical methods, namely Design of Experiments (DOE) and Response Surface Modelling (RSM). These tools permitted the identification and modelling of those process parameters whose variation would have the greatest impact on circuit performance. In the case considered, strained-Si circuit was more robust to process variations than the standard Si implementation.